The present invention relates to the manufacture of integrated circuits and, in particular, to a method and system for determining alignment or overlay error of integrated circuit fields within and between circuit layers made by a lithographic process.
Semiconductor manufacturing requires the sequential patterning of process layers on a single semiconductor wafer. Exposure tools known as steppers print multiple integrated circuit patterns or fields (also known as product cells) by lithographic methods on successive layers of the wafer. These steppers typically pattern different layers by applying step and repeat lithographic exposure or step and scan lithographic exposure in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits. Typically, 20-50 layers are required to create an integrated circuit. In some cases, multiple masks are required to pattern a single layer.
For the purposes of this application, the “alignment” and “overlay” of sequential patterning steps are distinguished as follows. Alignment is the position of an existing wafer target with respect to the exposure tool. Alignment error is the deviation of the location of the wafer target from its designed location, as determined by the alignment system of the exposure tool. Alignment to an existing layer (the aligned-to layer) is followed by the exposure that prints a new layer. On the other hand, overlay is the relative position among two or more patterns produced by successive exposures; most commonly, the relative position of the current layer and the aligned-to layer. Overlay error is the deviation of the relative position among patterns from their designed relative positions, as determined by an overlay metrology tool. To ensure circuit functionality, overlay errors must be minimized among all wafer patterns, consistent with the ground rules of the most critical circuit devices. As a rule of thumb, the overlay error between any pair of layers must be less than 40% of the minimum dimension. Thus, acceptable yield at the 70 nm node implies a layer-to-layer overlay tolerance of less than 30 nm. Achievement of such tight overlay tolerances over 300 mm wafers requires control of both layer-to-layer and within-layer overlay error, as described in U.S. Pat. Nos. 5,877,861 and 6,638,671.
Alignment and overlay both require specialized targets on each layer. The targets are placed in inactive areas of the wafer, either within the chip boundary or in the narrow dicing channel (kerf) that separates adjacent chips. In principle, alignment could use the prior layer components of the overlay target as align-to patterns. In practice, alignment and overlay metrology systems often require different target designs and locations. Overlay targets can be comprised of sub-patterns from both the same and different masks. The images are analyzed to determine the relative layer-to-layer and within-layer placement of the sub-patterns among the various mask layers printed on the wafer. Each determination of overlay error requires paired sub-patterns within a target whose relative position can be measured. From the overlay measurement perspective, therefore, the effective number of layers can be double the number of masks used in the patterning process. For this technical specification, the term layer is defined as any patterning step that requires a unique set of overlay sub-patterns.
One prior art approach has been not utilize a nested box, frame or bar target on successive lithographic layers as targets. Another option has been to utilize periodic or grating targets on successive lithographic layers.
Ideally, a target system to determine alignment and overlay error between lithographically produced integrated circuit fields on the same or different lithographic levels would be able to measure alignment and overlay error among many of the lithographic levels required to create an integrated circuit, and do so using a minimum of wafer surface area.